1. Field of the Invention
The present invention relates generally to eliminating predecode synchronization errors in a processor pipeline which processes instructions having a variety of lengths, and, more particularly, to advantageous techniques for padding program code such that a predecode engine correctly recognizes variable length instructions as instructions when predecoding an instruction string including embedded data.
2. Relevant Background
Today's processors typically support instruction sets having variable length instructions. For example, the ARM® instruction set consists of instructions having 32 bit lengths and instructions having 16 bit lengths. Pipelined processors which support variable length instructions may contain a predecode pipeline stage for partially decoding an instruction in order to simplify a subsequent decode stage and, thus, streamline the pipeline. A typical predecode pipeline stage checks, on a code line by code line basis, through program code, predecodes a code line, and writes the predecoded information into a cache along with the code line. Depending on the compiler used to create the program or object code, the program code may contain embedded data along with instructions.
Embedded data may coincidentally appear to resemble an instruction or a portion of an instruction. In such a case, a predecode engine would typically misinterpret embedded data. Thus, where the predecode engine incorrectly predecodes 16 bits of data as the first part of a 32 bit instruction, a subsequent 16 bit instruction might then in turn be interpreted as the second half of the 32 bit instruction so that invalid predecoded information would be stored in cache and the predecoding process might become out of synchronization for predecoding the next instruction. Typically, it would not be until a subsequent decode stage that the synchronization error is recognized. Such synchronization error results in processor delay and useless power consumption when attempting to recover from the predecode error.
Conventional approaches to the above problem include providing a recovery mechanism to resynchronize the predecode engine.